In a conventional method of manufacturing of a NAND non-volatile memory cell arrangement, a gate stack is formed on or above a substrate. The gate stack usually includes an oxide layer, a charge storage region, e.g., a floating gate layer or a charge-trapping layer structure, on or above the oxide layer and a gate region on or above the charge storage region.
In case of a floating gate memory cell arrangement, usually a dielectric layer structure is provided on or above the floating gate layer (usually made of polysilicon), the dielectric layer structure serving as a gate coupling dielectric. The gate region (in case of a floating gate memory cell arrangement a so-called control gate region) usually includes one or more polysilicon layers being connected to a word line.
In case of a charge-trapping memory cell arrangement, usually an oxide-nitride-oxide layer structure is provided on or above the substrate, the oxide-nitride-oxide layer structure being used for trapping electrical charge carriers. A gate region having one or more polysilicon layers is usually provided on or above the oxide-nitride-oxide layer structure. The gate region is usually connected to a word line as well.
In both cases, the material used for the word line is usually a refractory metal such as tungsten (W) or tungsten silicide (WSi).
In common methods of manufacturing the cells, the gate stack is structured and then, a self-aligned implantation of doping atoms into the substrate is carried out using the patterned gate stack as a mask. Subsequently, the implanted doping atoms are activated, thereby forming the source/drain regions. The activation is carried out using a high-temperature anneal at a temperature of about 1050° C. for about 10 seconds.